An integrated circuit tends to be more highly integrated. Accordingly, a scaling technique for a CMOSFET (Complementary Metal Oxide Semiconductor FET) used for the integrated circuit is widely known. The scaling is an industrial method for size reduction and performance improvement.
However, the following technical problems arise in the scaling. That is, the scaling (reduction of channel length, reduction of gate dielectric thickness and increase in impurity doping concentration) is accompanied by difficulty in controlling a short channel effect (SCE) and an off-state leakage current of a MOSFET.
In order to solve these problems, a MOSFET fabricated on Silicon-On-Insulator (SOI) substrate (a crystalline silicon substrate formed on an insulator film) has been developed. The SOI can reduce junction parasitic capacitance and the leakage current. Further, in order to solve the problems mentioned above, a Double-Gate MOSFET has been developed. One of practical embodiments of the Double-Gate MOSFET is a fin FET as described in each of Non-Patent Document 1 and Non-Patent Document 2. The fin FET is formed on the SOI substrate. Due to the very thin thickness, as illustrated in FIG. 9, of a body constituting a channel region, the fin FET operates in a fully depleted mode.
As another example of a solution for solving the problems, there is a Tri-Gate FET (Non-Patent Document 3). This Tri-Gate FET is also fabricated on the SOI substrate. Further, recently a fin FET formed on the bulk Si wafer substrate has been proposed (Non-Patent Document 4).
A fin structure disclosed in Patent Document 1 is formed by epitaxy. A fin structure disclosed in Patent Document 2 is also formed by epitaxy. In this case, an active area, where epitaxial growth occurs, is formed by a patterned layer (121) having the same thickness as epitaxial layer thickness.
[Patent Document 1]
Japanese Laid-Open Patent Application (Tokukai 2002-110963 (published on Apr. 12, 2002); corresponding to U.S. Pat. No. 6,525,403 B2)
[Patent Document 2]
Japanese Laid-Open Patent Application (Tokukai 2002-118255 (published on Apr. 19, 2002); corresponding to U.S. Patent Application Publication No. 2002/0011612 A1)
[Non-Patent Document 1]
IBM Journal of Research and Development, Vol. 46, No. 2/3, March/May 2002
[Non-Patent Document 2]
Hisamoto et al., FinFET-a Self-Aligned Double-Gate MOSFET Scalable to 20 nm, IEEE Trans. Vol. 47 (2000) 2320
[Non-Patent Document 3]
B. Doyle et al., “Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout,” 2003 Symp. VLSI Tech. Digest
[Non-Patent Document 4]
T. Park et al., “Fabrication of Body-Tied FinFETs(Omega MOSFETs), using BulkSi wafers,” 2003 Symp. VLSI Tech. Digest
The conventional fin FET formed on the SOI has a problem in that, in the view of IC production, the conventional fin FET is costly because the SOI wafer is more expensive than the bulk Si wafer generally used in IC fabrication. Further, the process of the fin FET formed on the SOI is so complex that a device size can be less freely chosen. Furthermore, a thicker fin results in a partially depleted device. This partially depleted device tends to cause such a problem that operation of a transistor becomes destabilized due to floating body effects, in which a body potential of a channel region section floats apart from a fixed potential such as earth and the like.
In order to solve the problem, fin FET fabrication on the bulk Si wafer is expected. Non-Patent Document 4 discloses the fin FET fabrication like this.
However, a device described in Non-Patent Document 4 requires an SiN layer covering a fin FET body surface. This SiN layer complicates the fabrication process and the formation of the SiN layer generates, in the fin FET body, mechanical stress that tends to result in a leakage current. This is a disadvantage of the device.
A fin FET structure described in each of Patent Document 1 and Patent Document 2 has such a problem that a large area is required for each junction section of a source region section and a drain region section. Accordingly, junction parasitic capacitance of the fin FET is the same level as that of the conventional FET formed on the bulk Si. Thus, the fin FET structure has such a problem that reduction in size cannot be accompanied by reduction of the parasitic capacitance.